| Student Name | School | Degree | Year | |
|---|---|---|---|---|
| Syeda Beenish | NBC | Undergraduate | Fourth | [email protected] |
| Syeda Beenish | NBC | Undergraduate | Fourth | [email protected] |
| Inter School Idea ? | Yes |
| Do you need expertises from another area: | No |
| If Yes please provide details of expertises you need: |
| Idea Name: | Optimization of Critical Path Delay in 16 bit RISC Processor |
| Slogan: | Optimization of Critical Path Delay in 16 bit RISC Processor |
| Supervisor Name: | Dr. Alamgir |
| Supervisor Designation: | Professor |
| Supervisor School: | NBC |
| Supervisor Department: | NBS |
| Contact number: | 0307 8272617 |
| Email ID: | [email protected] |
| Abstract: | |
| This project is about the design of a Floating-Point Unit (FPALU), integrating the FPU into the RISC-16 BIT processor, and synthesize the FPU design on the Field Programmable Gate Array. Hence, this project is required to develop an FPU which can perform the operation on floating point numbers especially and increased precision. The development project will start by studying the basics of multipli | |
| What is the unmet need in society that your idea will fulfill ? | |
| Details Not Available | |
| Who needs it ? How many would benefit ? | |
| Details Not Available | |
| How will the solution works | |
| Details Not Available | |
| Who are your competitors ? How is your solution different | |
| Details Not Available | |
| Status: | new |
| Entry Date & Time: | 2023-02-08 (2122) |